A) An Acc-ISA CPU executes the following instructions using 3-bit op-codes and 5-bit address or 2s complement data. Do the following:LD address //Acc ? Memory [address], read from LM2LD data //Acc ? data (a 2s complement number, sign extended)ADD data //Acc ? Acc + data (data is a 2 solutionspile.com

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A) An Acc-ISA CPU executes the following instructions using 3-bit op-codes and 5-bit address or 2’s complement data. Do the following:

LD address //Acc ? Memory [address], read from LM2

LD data //Acc ? data (a 2’s complement number, sign extended)

ADD data //Acc ? Acc + data (data is a 2’s complement number, sign extended)

SUB data //Acc ? Acc - data (data is a 2’s complement number, sign extended)

ADD (address) //Acc ? Acc + Memory[address]

STM (address) //M[address] ? Acc

SUB (address) //Acc ? Acc - Memory[address]

JMP address //PP ? address

JZ address

Draw a data path for the CPU assuming the DM has separate input and output bus as in the data path shown in Fig. 8.7. Do not include additional data paths not used by the instructions.

PLease Use this template and complete the missing parts: Chapter 8: Acc-ISA PI
Guide to HWH8: The Acc-ISA single-cycle data path to execute the program
8.3 An Acc-ISA CPU executes-th

Chapter 8: Acc-ISA PI Guide to HWH8: The Acc-ISA single-cycle data path to execute the program 8.3 An Acc-ISA CPU executes-the-following instruetions-using 3-bit op-codes and 5-bit address or 2's complement data. Do the following: LD address

// A CC ?

Memory [address], read from LM2 LD data

// A C c ?

data (a 2 's complement number, sign extended) ADD data

/ A C c ? A CC +

data (data is a 2 's complement number, sign extended) SUB data

// A C c ? A C c

-data (data is a 2 's complement number, sign extended) ADD (address)

// A c C ? A CC +

Memory[address] STM (address) //M[address]

? AcC

SUB (address)

// A C c ? A CC

- Memory[address] JMP address

// PP ?

address JZ address

II PP ? address (if result of the operation was zero). a) Draw a data path for the CPO assuming the DM has separate input and output bus as in the data path shown in Fig. 8.7. Do not include additional data paths not used by the instructions. (15 pts)

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