(Solved): a. Design an ASM chart with RTL operations in this chart. Datapath and contro ...

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a. Design an ASM chart with RTL operations in this chart. Datapath and control unit are not separated. Start the chart first by loading Data onto R1 and R2 so that they have values to be swapped. In the testbench, make sure Data is different in the first two clock cycles. Stay here is $w==0$. Start when $w==1$ b. Write and simulate a Verilog module to implement this design