(b) (7 pts) DRAM data needs to be refreshed regularly because there is leakage current from
the storage node. Assume the only leakage current path from the DRAM storage node is
represented by R_(leakage )(=10^(13)\Omega ) as shown in the figure below. If the cell storage capacitance
(Ccell) is 10f(F)=10^(-14)(F) and the cell initial voltage is Vdd, how long will it take for the
cell storage voltage value to become Vd(d)/(2) even if the access transistor is turned off?