c) For the data path shown in Figure 1 and a clock cycle time of 1000ps, determine which latches borrow time and if any setup time violations occur for the propagation delay scenarios in (i) & (ii). Assume zero clock skew and the latch delays are accounted for in the propagation delay "D"s in (i) and (ii). (i) D1=550ps,D2=580ps,D3=450ps,D4=200ps solutionspile.com

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c) For the data path shown in Figure 1 and a clock cycle time of 1000ps, determine which latches borrow time and if any setup time violations occur for the propagation delay scenarios in (i)  & (ii). Assume zero clock skew and the latch delays are accounted for in the propagation delay &#34;D&#34;s in (i) and (ii). (i) D1=550ps,D2=580ps,D3=450ps,D4=200ps (ii) D1 =300ps,D2=600ps,D3=400ps,D4=550ps Figure 1 solutionspile.com

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