Consider an application which has an instruction mix of 40% ALU and logical operations • • 30% load and store • 20% branch • 10% jump instructions. Baseline CPI is 1. Memory hierarchy is as follows: A 2-way set associative L1 data cache with a miss rate of 5%. • • A direct-mapped L1 instruction cache with a miss rate of 3%. • The miss penalty of 50 cycles for both instruction and data caches. • A data cache uses a write-back policy and 40 % of victim blocks are dirty.