(Solved): Consider the attached MIPS single-cycle data-path. Assume that it is required to add to the instru ...

Consider the attached MIPS single-cycle data-path. Assume that it is required to add to the instruction set architecture the following instruction: \[ \text { loop } r 1, r 2 \text {, offset } \] Let this instruction be of I-type with the format of This is a branch instruction that increments register \( \mathbf{r} \mathbf{1} \) by \( \mathbf{1} \), and compares it to \( \mathbf{r} \mathbf{2} \). If these two values are not equal then the \( P C \) is set to \( P C+ \) offset \( <<2 \), otherwise \( P C \) is set to PC+4. The instruction has the same effect as sequentially executing the following two instructions on the MIPS architecture: \[ \text { addi } \mathrm{r}, \mathrm{r} 1,1 \] bne \( r 1, r 2 \), offset A/ On the single-cycle data-path, draw clearly any necessary data-path(s) and modifications that are required for executing the loop instruction. Note: In the single-cycle processor design, it is not allowed to use any component more than once during the instruction execution. Instead, it is allowed to duplicate the components.