(Solved): Consider the following 4 bits up counter circuit below then answer the questions: 1. Write Verilog ...

Consider the following 4 bits up counter circuit below then answer the questions: 1. Write Verilog data flow code for half Adder (2 points) 2. Write Verilog behavioural code for $D$ flip flop with asynchronous reset (3 points) 3. Write structural Verilog code for the counter circuit by instantiating the half adder and the D flip flop you built in questions 1 and 2 above. ( 5 points) Submit your answers in one notepad file