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(Solved): could you solve the question with proper formula step by step. Question 5 : Consider the following ...
could you solve the question with proper formula step by step.
Question 5 : Consider the following synchronous circuit. Assume all logic gates (NAND2, NOR2) have a
propagation delay of 2 ps . The parameters for the flip-flop banks are given below. The minimum clock period
T_(MIN) for the circuit to operate correctly is given by:
Flip-flop bank 1
Combinational
Circuit
Flip-flop bank 2
Flip-flops bank 1: t_(p(CLK->Q))=1ps,t_(setup )=4ps,t_(hold )=3ps
Flip-flops bank 2: t_(p(CLK->Q))=4ps,t_(setup )=1ps,t_(hold )=2ps
A
T_(MIN)=10ps
T_(MIN)=7ps
T_(MIN)=9ps
D T_(MIN)=8ps