Design a radix-4 Booth multiplier for operand length of 6 bit each. The multiplier should take two 6-bit numbers as input and provide a 12-bit product as the output. Guidelines: 1. The multiplier can be designed by modifying the signed multiplier. 2. Provide a complete design for the circuit that supplies the control signals to the multiplexer. 3. Design the controller as an FSM. 4. Implement the components in VHDL and then integrate the components using port maps to build the full multiplier. 5. Synthesize the multiplier onto FPGA.