Given the data path and the state transition diagram of a digital circuit. 1. Obtain the verilog model of the datapath. 2. Obtain the verilog model of the control 3. Combine datapath and control in a top module. 4. Simulate the circuit for inputs X=170Y=8 Reset resets counter and 16-bit register Load, loads 8-bit registers, Inc increments counter solutionspile.com

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Given the data path and the state transition diagram of a digital circuit. 1. Obtain the verilog model of the datapath. 2. Obtain the verilog model of the control 3. Combine datapath and control in a top module. 4. Simulate the circuit for inputs X=170Y=8 Reset resets counter and 16-bit register Load, loads 8-bit registers, Inc increments counter by 1. solutionspile.com

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