(Solved): Make a test bench for this Verilog code, and show waveform result: Implement the multifunction regi ...

Make a test bench for this Verilog code, and show waveform result:

Implement the multifunction register.

a. Output: Q[3:0] (re-evaluated only at positive edge of clock. Default: 0000)

b. Input : clk, Data: In[3:0], Sh_in

c. Control Signal :

i. Rst( if ‘1’: Q[3:0]=0000)

ii. Ld (if ‘1’, Q[3:0] =In[3:0])

iii. Shl (if ‘1’: Q[3:1]=Q[2:0], Q[0]=Sh_in)

iv. Shr (if ‘1’: Q[2:0]=Q[3:1], Q[3]=Sh_in)

4. Write testbench where you take 4 numbers A, B, C, D.(each 4 bit).

a. Add A and B,

b. compare A and B; A and C; A and D.

c. In your multifunction register load A in parallel

d. In your multifunction register serially make Q= 0111 by right shifting e. In your multifunction register serially make Q= 1110 by left shifting