(Solved):   need the vhdl code and constraints file to use for a Basys 3 trainer Board Project: EPIC D ...

 

need the vhdl code and constraints file to use for a Basys 3 trainer Board

Project: EPIC Design a 7-segment decoder that determines two-bit logical input (using the switches on the BASYS 3 trainer board), and generates output on the 7-segment display as shown in the following table: $1 Display So 7-segment 10 If both switches are OFF, the 7-segment has to display capital letter 'E. . If the switch So is ON and S? is OFF, the 7-segment has to display capital letter 'P If the switch So is OFF and S? is ON, the 7-segment has to display capital letter | . If both switches are ON, the 7-segment has to display capital letter C. To achieve this, you have to derive the Boolean expression for each segment of the 7-segment display: a, b, c, d, e, f, and g by using the method of your choice (Karnaugh map, minterm or maxterm). 9 WOJUJ E 0