(Solved): need help translating verilog code to gate schematic. thank you. 2. Draw the schematic of the log ...

need help translating verilog code to gate schematic. thank you.

2. Draw the schematic of the logic circuit described by the Verilog code below: module pie $$(x,y,a,b,c)$$; input $$a,b,c;$$ wire $$t1,t2;$$ output $$x,y;$$ xor $$\#2\times 1(t1,a,b)$$; not $$\#1n1(x,t1);$$ and $$\#3a1(t2,x,c)$$; or $$\#301(y,t2,b)$$; endmodule (b) What is the critical path of this design from primary inputs to outputs and what is the delay of the critical path in terms of unit delay?