
Pipelining in computer architecture is a technique where multiple instructions are overlapped in execution. It's much like an assembly line in a factory, where different stages of production are handled simultaneously but at different stages of completion. Each stage in a pipeline completes a part of an instruction; as one instruction is being executed, another is being decoded, and yet another is being fetched from memory. Program In the context of MIPS architecture, a pipeline hazard is a situation that causes the next instruction in the pipeline to either stall or be executed incorrectly. These hazards are generally categorized into three types: data hazards, control hazards, and structural hazards. Data hazards occur when instructions that are close together in a program depend on the same data. Control hazards arise from the pipelining of branches and other instructions that change the PC. Structural hazards happen when hardware cannot support all possible combinations of instructions in simultaneous overlapped execution. For example, consider these two MIPS assembly code lines: 1. 'ADD R1, R2, R3' (This instruction adds the contents of R2 and R3 and stores the result in R1) 2. 'SUB R4, R1, R5' (This instruction subtracts the contents of R5 from R1 and stores the result in R4 ) Question: What type of hazard is being referred to in this scenario, and what strategies can be employed to mitigate it? Create a diagram to visually illustrate the hazard and present ways to address it. (Hints: Introduce a control signal, and consider the addition of extra wires to reduce dependency, this is a widely studied problem).