(Solved): PROGRAMMING USING QUARTUS HERE IS THE CODE I USED AND COMPILATION OF ERRORS ...

PROGRAMMING USING QUARTUS

HERE IS THE CODE I USED AND COMPILATION OF ERRORS I AM RECIEVING PLEASE HELP I DONT NOT KNOW WHAT I AM DOING WRONG

PRIORITY ENCODER You will use the priority encoder to fully explore the two concurrent statements covered in class, the WHEN ELSE and the WITH/SELECT/WHEN statements. The truth table for a priority encoder is given below. The $$\mathbf{d}$$ at the inputs means "don't care". Using a WHEN ELSE statement. Write the code to implement a priority encoder using the WHEN ELSE statement. There are several ways to implement this decoder using the WHEN ELSE statement. You will write several programs using that statement. Program \#1 The WHEN ELSE statement checks the conditions in the order listed. So, if you think about that, the easiest way is to handle the truth table is to: - first check if D7 is a 1 (make that the first condition checked in the statement), then - check if D6 is a 1 (make that the second condition checked in the statement), then - check if D5 is a 1 and so forth, i.e., For instance, the first condition checked would be: $$y<=$$ "111" when $$d(7)=1^{?}$$ ' else .... Note that this line assumes the input $$d$$ and the output $$y$$ are both of type std_logic_vector. Write the program in Quartus and just do the "Analysis and Synthesis". Get the synthesis result. To view the synthesis result: Tools > Netlist Viewer $$>\mathbf{RTL}$$ Viewer Copy and paste your resulting program and the resulting hardware (the synthesis result) onto a Word file. Type ID Message 4 18236 Number of processors has not been specified which may cause over loading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS (i) 20030 para7le 1 compilation is enabled and will use 8 of the 8 processors detected - (1) 12021 Found 2 design units, including 1 entities, in source file program_1.vhd ( 10309 vHDL Interface Declaration error in Program_1.vhd(18): interface object " $$y$$ " of mode out cannot be read. change object mode to buffer. ? 10327 vHDL error at Program_1.vhd(18): can't determine definition of operator ""<=" $$?$$ :- found 0 possible definitions ( 10309 vHDL Interface Declaration error in program_1.vhd(17): interface object " $$y$$ " of mode out cannot be read. Change object mode to buffer. \& 10327 VHDL error at Program_1.vhd(17) : can't determine definition of operator ""<=" -- found 0 possible definitions Q 10309 vHDL Interface Declaration error in Program_1.vhd(16): interface object " $$y$$ " of mode out cannot be read. Change object mode to buffer. $$?10327$$ VHDL error at Program_1.vhd(16): can't determine definition of operator ""<=" -- found 0 possible definitions ( $$10309\mathrm{vHDL}$$ Interface Declaration error in Program_1. vhd(15): interface object "y" of mode out cannot be read. Change object mode to buffer. $$?10327$$ vHDL error at Program_1.vhd(15) : can't determine definition of operator ""<=" $$?$$ vound 0 possible definitions ? 10309 vHDL Interface Declaration error in Program_1.vhd(14): interface object "y" of mode out cannot be read. Change object mode to buffer. \& 10327 VHDL error at Program_1.vhd(14): can't determine definition of operator ""<=" $$?$$ :- found 0 possible definitions ? 10309 vHDL Interface Declaration error in Program_1.vhd(13): interface object " $$y$$ " of mode out cannot be read. Change object mode to buffer. $$?10327$$ VHDL error at Program_1.vhd(13): can't determine definition of operator ""<=" $$?$$ found 0 possible definitions ( ) $$10309\mathrm{vHDL}$$ Interface Declaration error in Program_1.vhd(12): interface object " $$y$$ " of mode out cannot be read. Change object mode to buffer. 10327 VHDL error at Program_1.vhd(12): can't determine definition of operator ""<=" -. found 0 possible definitions Quartus Prime Analysis \& Synthesis was unsuccessful. 14 errors, 1 warning 293001 Quartus Prime Fu11 Compilation was unsuccessful. 16 errors, 1 warning 1ibrary IEEE; use IEEE.std_logic_1164.a11; ENTITY verify IS PORT(d: IN std_logic_vector (7 DOWNTO 0); y: OUT std_logic_vector (2 DOWNTO 0) ); end verify; --end verify; ARCHITECTURE encoding of verify IS gbegin $$y<=$$ "111" WHEN d(7)= '1" ELSE $$y<="110^{??}$$ WHEN $$d(6)=$$ " 1 " ELSE $$y<=$$ "101" WHEN d(5)="1" ELSE $$y<="100$$ " WHEN $$d(4)=$$ ' 1 " ELSE $$y<=$$ "011" WHEN d(3)='1" ELSE $$y<="010^{??}$$ WHEN $$d(2)=$$ ' 1 " ELSE $$y<=$$ "001" WHEN d( 1$$)=$$ "1 " ELSE $$\mathrm{y}<=$$ "000" WHEN $$\mathrm{d}(0)={}^{?}1$$ '; end encoding;