Use Verilog HDL code Coding Exercise 1: Design a 4-bit Adder/Subtractor like the figure seen below. You are to design the adders using user-defined primitives while the rest of the components are using the structural modeling. The ( S ) input switches between the adder and subtractor; if ( S=1 ), then the circuit is a subtractor else it will f solutionspile.com

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Use Verilog HDL code  Coding Exercise 1: Design a 4-bit Adder/Subtractor like the figure seen below. You are to design the adders using user-defined primitives while the rest of the components are using the structural modeling. The  ( S  ) input switches between the adder and subtractor; if  ( S=1  ), then the circuit is a subtractor else it will function as an adder. Figure  ( 6.13  ) shows a diagram of the 4-bit Adder/Subtractor circuit.: solutionspile.com

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