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(Solved): Using the basys3 development board and the Da2 p-mod. It is the intention of these following codes t ...
Using the basys3 development board and the Da2 p-mod. It is the intention of these following codes to produce a sin waveform and output that on to an oscillscope.
![module AHBPmod( input wire HCLK, input wire HRESETn, input wire [31:0] HADDR, input wire [1:0] HTRANS, input wire [31:0] HWDA](https://media.cheggcdn.com/study/448/448d6a68-edf7-4652-9b71-a775dac887c8/image)
![\( 50,53,55,58,61,63,66 \),
void DAC_Write(int value)\{
static const unsigned int mask[] \( =\{0 \times 0001,0 \times 0002,0](https://media.cheggcdn.com/study/3b4/3b48fade-104c-4d5e-baf3-35652b6f67fd/image)
module AHBPmod( input wire HCLK, input wire HRESETn, input wire [31:0] HADDR, input wire [1:0] HTRANS, input wire [31:0] HWDATA, input wire HWRITE, input wire HSEL, input wire HREADY, //Output output wire HREADYOUT, output wire [31:0] HRDATA. output wire [3:0] DA2 ;i reg [31:0] last_HADDR; reg [1:0] last_HTRANS; reg last_HWRITE; reg last_HSEL; assign HREADYOUT = 1'b1; // Set Registers from address phase always @(posedge HCLK) begin if (HREADY) begin last_HADDR HADDR; last_HTRANS HTRANS; last_HWRITE HWRITE; last_HSEL HSEL; end end always @(posedge HCLK) begin I/DA2 logic //1khz SINE WAVE J/aT LEAST DOUBLE THE NUMBER OF SAMPLES //1KHZ AT LEAST 2000 I/GENERATE BY LOOK UP TABLE //bIG FAT ARRAY (in C) first element in list is sine at time //2nd element in array is sine at itmeslice 1 //3rd Sine of timeslice I/Work out timeslice IITimeslice look at clock fequency //Do some maths for sione wave frequency [/For loop through samples IITime for loop through sample
always @(posedge HCLK) begin //DA2 logic //1khz SINE WAVE //aT LEAST DOUBLE THE NUMBER OF SAMPLES //1KHZ AT LEAST 2000 //gENERATE BY LOOK UP TABLE //bIG FAT ARRAY (in C) first element in list is sine at time //2nd element in array is sine at itmeslice 1 //3rd Sine of timeslice //Work out timeslice //Timeslice look at clock fequency //Do some maths for sione wave frequency //For loop through samples //Time for loop through sample
, void DAC_Write(int value)\{ static const unsigned int mask[] O/SYNC I/SYNC I/for i in 0 to 15 II clock goes high II datawire value bit i II clock falling edge \}