(Solved): verilog please one file Operation 2: Using the concept of Full-Adder, perform the following additio ...

verilog please one file

Operation 2: Using the concept of Full-Adder, perform the following addition: Output $$=($$ Odd value of $$X)+($$ Even Value of $$Y)$$ Note: the circuit should allow 0 as even value for $$Y$$. Where $$X\&Y$$ are 3-bits binary inputs such as: $$X$$ takes the lest 3 bits from the input $$([[2],I[1],I[0])$$, such as $$X[\mathrm{2..0}]$$ will be as the following: - $$\mathrm{X}[2]=\mathrm{l}[2]$$ - $$\mathrm{X}[1]=?[1]$$ - $$\mathrm{X}[0]=I[0]$$ $$Y$$ takes the most 3 bits from the input $$(I[5],I[4],I[3])$$, such as $$Y[\mathrm{2..0}]$$ will be as the following: - $$\mathrm{Y}[2]=?[5]$$ - $$\mathrm{Y}[1]=?[4]$$ - $$\mathrm{Y}[0]=I[3]$$ Design the problem in Quartus as block diagram schematic or Verilog then verify using waveform. Note: All Operations must be Block Symbols to be combined as final Design file (Block diagram).